Wafer Level Ball Grid Array (WLB) technology has been used to build integrated circuit packages on silicon wafers. In WLB packages, the interconnects are in a fan-in arrangement. In contrast, Embedded Wafer Level Ball Grid Array (eWLB) technology is used to build packages on an artificial wafer made from singulated chips and a casting compound. Typically, the die is mounted face down on a support by a pick and place (PnP) tool, over-molded, and cured. The support is then removed and interconnects are built on the exposed face of the die in a fan-out arrangement.
The fan-out arrangement provides more space for interconnect routing than in traditional WLB packages. However, current eWLB technology has several drawbacks. First, the pick and place (PnP) tools used to place the components are expensive and have a limited throughput capacity, and not all components need the same placement accuracy. In addition, the components can shift during the molding and curing process. High density/high bandwidth routing is not viable due to poor die (component) to die (component) alignment accuracy. Next, the placement of dies or other components onto die attach film (DAF) on the support by PnP tools can leave voids trapped under the die or component. Finally, the interconnects are made with either laser drilled vias or photo defined vias, which can be suboptimal in cost or performance.